1. Field of the Invention
The present invention relates in general to a semiconductor memory and, in particular, to a non-volatile Content Addressable Memory (CAM).
2. Description of the Related Art
Unlike conventional memories, CAMs include a plurality of CAM cells that are addressed in response to their content, rather than by a physical address. Words stored in a CAM are accessed, i.e., univocally identified, by applying corresponding data values to input terminals of the CAM. In response to applied data values, a match line of the CAM is driven so as to assert or de-assert an associated match signal, indicating whether or not a stored word matches the applied data values.
CAMs are useful in many applications, such as search engines, in which a list of data values in predetermined order is searched to identify a specific word in the CAM. By identifying which location of the CAM is coupled to a match line driven to assert the match signal, the specific word is identified.
Two types of CAM cells are typically used in CAMs: binary CAM cells and ternary CAM cells. A binary CAM cell can store a high logic value or a low logic value. A ternary CAM cell can store one of three values: a high logic value, a low logic value or a “don't care” value. When the logic values stored in the binary or ternary CAM cells of a CAM location match applied data values, then the match line coupled to that location is driven so as to assert the match signal. Otherwise, when the logic values stored in the binary or ternary CAM cells of a CAM location do not match the applied data values, then the coupled match line is driven so as to de-assert the match signal. In addition, a ternary CAM cell storing a “don't care” value provides a match (or, alternatively, a mismatch) condition irrespective of the data value applied thereto.
Both binary and ternary CAM cells can be either volatile or non-volatile. In particular, volatile CAM cells were initially implemented by exploiting the architecture of static RAM (SRAM) cells and adding transistors for realizing an output of the CAM cell connected to the match line coupled thereto. Recently, volatile CAM cells have been developed based on the dynamic RAM (DRAM) architecture, for reducing the semiconductor area occupied by the relatively high number of transistors employed in a CAM cell based on an SRAM architecture.
The volatile CAM cells, based on SRAM or DRAM cells, have a low access time (lower in SRAM than in DRAM-based CAM cells), but their content is lost during power-down. Consequently, the volatile CAM cells need be re-loaded at every power-on of the CAM, and a separate memory device of non-volatile type, such as a hard disk or an EPROM memory has to be used as a back-up storage unit for the volatile CAM.
The use of two distinct semiconductor memories (distinct chips) is disadvantageous, because very complex and expensive. A wide area on a printed circuit board is to be reserved, additional sockets and interconnections between the two memories are to be provided.
Non-volatile CAMs have been proposed. For example, U.S. Pat. No. 6,317,349 B1 discloses an architecture of ternary non-volatile CAM cell, including two floating gate transistors of the type normally used in flash memories. A floating gate transistor is non-volatily programmed by injecting charges into the floating gate, so as to modify its threshold voltage: for example, a high threshold voltage can be associated with a high logic value, while a low threshold voltage can be associated with a low logic value, or vice versa. This non-volatile CAM cell preserves its content also during power-down and moreover permits the use of a smaller number of transistors in respect to a CAM cell based on SRAM architecture.
In a CAM, the operation of searching a given data word (search operation) needs a preset phase, in which each match line is precharged to a prescribed preset voltage. When a searched word matches the word stored in a CAM location, the match line coupled thereto remains at the preset voltage, while a variation of the voltage at a match line is read as a mismatch. A drawback of the non-volatile CAM cell architecture described in U.S. Pat. No. 6,317,349 B1 is a consequence of the flow of leakage currents through the floating gate transistors with low threshold voltage during the search operation. In a mismatch condition during the search operation, if a number of CAM cells of the same CAM location conduct leakage currents, it may happen that the voltage at the match line does not vary sufficiently to be read as a mismatch. This problem is significant when the threshold voltage of the floating gate transistors is low (a lower threshold voltage implies a greater leakage current), but in any case the leakage currents imply an excessive power consumption. Furthermore, during the search operation it may happen that only one CAM cell of a CAM location shows a mismatch, while all the other CAM cells of the same location show a match. The discharge of the match line coupled to this location from the preset voltage can be very slow and in many applications auxiliary circuits might be necessary, to be associated with such a non-volatile CAM for speeding up the discharge of the match lines and, consequently, the search operation.
The Applicant also observes that a programming operation of floating gate transistors requires a relatively long time, and a preliminary block erasing operation is necessary. The erasing operation can be critical because of the problem of regulating the threshold voltage of the floating gate transistors for limiting the leakage threshold voltage.